1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly, to a semiconductor device having a transistor with a vertical gate electrode, and a method of fabricating the same.
2. Discussion of Related Art
Semiconductor device integration has followed Moore's law or Hwang's law, which are observations that a degree of integration of semiconductor devices tends to double every 18 months or 1 year. These observations are expected to hold true into the future. To continue increasing the degree of integration, a planar area occupied by electronic elements of the semiconductor devices needs to be reduced. This reduction is restricted by the various characteristics that the electronic elements need to satisfy.
Regarding metal-oxide-semiconductor (MOS) transistors, a short channel effect is a typical restriction associated with the reduction of integration. The short channel effect occurs as a channel length of a transistor (e.g., a distance between a source electrode and a drain electrode) becomes narrower. The short channel effect degrades the characteristic of transistors, similar to a punch-through, a drain induced barrier lowering (DIBL), and a subthreshold swing. In addition, the reduction in the channel length of the transistor causes an increase of a parasitic capacitance between a substrate and source/drain electrodes, the increase of a leakage current, etc. Due to these problems, the reduction in the channel length of the transistor is restricted.
In the case of a planar MOS transistor, the degree of integration of a semiconductor device can be increased by reducing a channel width of a transistor. A channel width (W) is proportional to a drain current (Id) as given by equation (1), and the reduction of the channel width will decrease a current driving capability of the transistor.
                              I          d                =                              W            L                    ⁢                      f            ⁡                          (                                                V                  G                                ,                                  V                  T                                ,                                  V                  DS                                            )                                                          (        1        )            
where L is a channel length.
Flash memory includes a gate insulating layer of a uniform thickness between a floating gate electrode and a semiconductor substrate. Due to the uniform thickness of the gate insulating layer, read and write operational characteristics of the flash memory may be limited. For example, the thickness of the gate insulating layer may be increased so as to increase an information storage capacity, however the read and write operational characteristics are negatively effected by the increased thickness of the gate insulating layer. Accordingly, the thickness of the gate insulating layer is selected to balance the storage capacity and read and write characteristics. A unit cell of a nonvolatile memory device, such as an EEPROM, includes a select transistor and a cell transistor to substantially overcome this limitation. However, since the unit cell of the EEPROM has two transistors, an area of the unit cell is increased.
In the conventional planar MOS transistor, a tradeoff relationship exists between the improvement of the characteristics of the transistor and the increase of the degree of integration thereof. Accordingly, there is a demand for a transistor structure that can satisfy the two technical needs of improved device performance and increased integration.